1. Field of the Invention
The present invention relates to a block access memory and, more specifically, it relates to an improved accessing for enhancing an operating efficiency of a block access memory.
2. Description of the Prior Art
Recently, a semiconductor memory device has come to be implemented with larger capacity and it has been desired to enhance the data transfer rate in order to provide high speed operation. In order to improve the data transfer rate, a block access memory as shown in FIG. 1 has come to be used in which data input/output is carried out serially between the shift register and a data input/output portion, and data transfer is simultaneously carried out between the shift register and an entire row of memory cells (memory cells connected to one word line).
Referring to FIG. 1, a conventional block access memory comprises an address buffer 7 which receives externally applied external address signals A0 to A7 and generates complementary address signals A0, A0 to A7, A7; a refresh address counter 8 which successively generates refresh row addresses for designating the row to be refreshed; a REF buffer 9 which receives an externally applied external refresh signal Ext. REF for designating the refresh cycle and generates signals REF and REF for transmitting either the complementary address A0 to A7, A0 to A7 or the refresh row address from the refresh address counter 8; a switch SW1 which turns on in response to the signal REF from the REF buffer 9 for transmitting an output of the address buffer 7 to the row decoder 1; a switch SW2 which turns on in response to the signal REF from the REF buffer 9 for transmitting the refresh row address from the refresh address counter 8 to the row decoder 1; a row decoder 1 which receives and decodes a row address applied from the address buffer 7 or from the refresh address counter 8 and selects accordingly one word line; a plurality of memory cells 4 arranged in rows and columns, each storing information; a plurality of word lines 2 for selecting one row of the plurality of memory cells 4; a plurality of bit lines 3 to each of which is transmitted the information of a memory cell connected to the word line which is in turn selected by the output of the row decoder 1; a sense amplifier group 5 provided corresponding to each of the bit lines 3 for detecting/amplifying the information on the bit lines; a shift register 6 which simultaneously receives the signals from the sense amplifier group 5 in response to the clock signal .PHI.20 and transmits the received data successively to the data output buffer 10 in response to clock signals .PHI.1 and .PHI.2; and an output buffer 10 which outputs the information from the shift register 6 serially as the output data D.sub.OUT. In FIG. 1, the memory cell array MA is structured with 256 rows.times.256 columns as an example. The shift register 6 has its output portion and the input portion connected together to form a loop. The sense amplifier group 5 is activated in response to the sense amplifier activating signal SE.
FIG. 2 shows the structure of the sense amplifier group 5 and the shift register 6 shown in FIG. 1 in more detail. Referring to FIG. 2, the sense amplifier group 5 is constituted by 256 sense amplifiers 5-1 to 5-256 provided corresponding to each of the bit line pairs. Each of the sense amplifiers 5-1 to 5-256 is constituted by two switch transistors Tr1 and Tr2 having their gates and drains cross connected and is activated in response to the sense amplifier activating signal SE to differentially amplify the potential on the bit lines using the level of a bit line to which the non-selected memory cell is connected as a reference potential, and outputs a potential on the bit line BL. As for the bit lines, a bit line to which a selected memory cell is connected and a reference bit line which applies the comparison reference potential with respect to the potential on that bit line are arranged in pairs. The shift register 6 is constituted by 256 stages of unit shift registers 6-1 to 6-256. Each of the unit shift registers 6-1 to 6-256 is constituted by two stage inverters I1 and I2 and a switch transistor T1 connected between these inverters and which turns on in response to the clock signal .PHI.1. A switching transistor T2 which turns on in response to the clock signal .PHI.2 is provided between adjacent unit shift registers. The outputs of the sense amplifiers 5-1 to 5-256 are transmitted to the input portions of respective unit shift registers 6-1 to 6-256 through the switching transistors 11-1 to 11-256 which turn on in response to the clock signal .PHI.20.
FIG. 3 is a waveform diagram showing the data reading operation in a conventional block access memory shown in FIG. 1. The operation of a conventional block access memory will be hereinafter described with reference to FIGS. 1 to 3.
First, for example, an external RAS signal (not shown) which is a basic operation timing signal becomes activated and external address signals A0 to A7 are taken into the memory chip and applied to the address buffer 7. In the normal data reading cycle, the external refresh signal Ext. REF is at a low level. Therefore, the signal REF is at a high level, the signal REF is at the low level, and the switch SW1 is turned on while the switch SW2 is turned off. The complementary addresses A0, A0 to A7, A7 generated in the address buffer 7 are transmitted to the row decoder 1 through the switch SW1. Thereafter, one word line is selected by the row decoder 1 which is designated by the address signals A0, A0 to A7, A7, the potential of the selected word line WL rises and one row of memory cells is selected. Consequently, the potential change corresponding to the information contained in the memory cell connected to the selected word line WL appears on each of the bit lines 3. Thereafter, the sense amplifier activating signal SE falls and the sense amplifier group 5 (5-1 to 5-256 of FIG. 2) is activated and differentially amplifies the potential on each bit line pair BL and BL using the level bit line to which the non-selected memory cell is connected as a reference potential. Then, the clock signal .PHI.20 rises and the switch transistors 11-1 to 11-256 turn on and the information from each of the sense amplifiers 5-1 to 5-256 is simultaneously transmitted to the input portion of each of the unit shift registers 6-1 to 6-256 of the shift register 6. The information transmitted to the shift register 6 is successively transmitted to the data output buffer 10 serially bit by bit in response to the clock signals .PHI.1 and .PHI.2, and the serial 256 bit data is read through the data output buffer 10 as the output data D.sub.OUT. When one cycle (serial read cycle) is completed, the potential of the selected word line WL falls and the sense amplifier activating signal SE rises, and the external refresh signal Ext. REF becomes high level so that the signal REF becomes high level and the signal REF becomes low level. Consequently, the refresh row address from the refresh address counter 8 is transmitted to the row decoder 1 through the switch SW2, thereby starting the refresh cycle. One word line is selected corresponding to the refresh row address which is decoded by the row decoder 1, the selected word line level rises and the information contained in the memory cells connected to the selected word line is transmitted to respective bit lines. Thereafter, the sense amplifier activating signal SE becomes low level and the sense amplifier group 5 is activated to differentially amplify the potential difference on each bit line pair, establishing the potential level on the bit lines 3. Thereafter, by lowering the potential of the selected word line, the potential level on each bit line is re-written in each memory cell, and the refresh of the memory cell information is completed. On this occasion, the refresh address counter 8 outputs a refresh row address and applies the same to the row decoder 1 and thereafter increments or decrements the address.
The operation timing of the refresh address counter 8 is given by, for example, the signal REF and the increment or decrement of the refresh row address is automatically carried out in the counter 8.
The data writing cycle is carried out with the same timing as in the data reading and data is serially inputted to the shift register 6 from a data input buffer, which is not shown. As for the operation in data writing, the operation timing is similar to that in reading, except that the flow of the stream of data is reversed to that in the reading. Namely, the description of the operation of data reading is directly applied when the reading buffer 10 of FIG. 1 is replaced with a writing (or data input) buffer and the data is assumed to flow from the writing buffer to the shift register and to the memory cells of one row.
Since a conventional block access memory is structured as described above, a refresh cycle must be interposed between the normal data reading cycle or the data writing cycle in order to refresh the memory cells, so that the operating efficiency of the block access memory is lowered.
A memory device in which the data transfer is carried out between memory cells of one row and the shift register is disclosed in U.S. Pat. No. 4,541,075 to Dill et al., entitled "RANDOM ACCESS MEMORY HAVING A SECOND INPUT/OUTPUT PORT", U.S. Pat. No. 4,044,339 to Berg, entitled "BLOCK ORIENTED RANDOM ACCESS MEMORY" and in an article "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications" by R. PINKHAM et al., IEEE Journal of Solid-State Circuits Vol. SC-19, No. 6, December 1984, pp. 999-1007.
These prior arts disclose a structure in which serial data transfer is carried out between the shift register and the exterior and the simultaneous data transfer of all of the data bits is carried out between the shift register and the memory cells of one row in the DRAM. However, there is no consideration for the existence of a refresh cycle which is an essential operation cycle in the DRAM in these references.